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Verilog Design Flow
Design, implement, and verify Verilog/SystemVerilog modules with spec-driven development, self-checking testbenches, and automated simulation workflows
Legitimate Verilog/SystemVerilog design and simulation workflow skill with no security concerns. All shell usage is documented EDA tool execution (VCS, Xrun, Icarus) and VCD analysis uses standard open-source library.
可以安装
This skill is safe to use. No security concerns identified.
| 资源类型 | 声明权限 | 推断权限 | 状态 | 证据 |
|---|---|---|---|---|
| 文件系统 | READ | READ | ✓ 一致 | SKILL.md declares file creation for .v/.sv files; scripts read VCD files |
| 命令执行 | WRITE | WRITE | ✓ 一致 | SKILL.md:82-95 documents subprocess calls to vcs, xrun, iverilog; scripts/simula… |
| 网络访问 | NONE | NONE | — | No network activity detected |
| 环境变量 | NONE | READ | ✓ 一致 | scripts/simulate.sh:26-29 uses 'command -v' for tool detection (safe) |
| 凭据 | NONE | NONE | — | No credential access found |
| 敏感路径 | NONE | NONE | — | No sensitive path access (~/.ssh, ~/.aws, .env) |
目录结构
4 文件 · 19.0 KB · 641 行 Markdown 2f · 430L
Shell 1f · 124L
Python 1f · 87L
├─
▾
references
│ └─
vcd-analysis.md
Markdown
├─
▾
scripts
│ ├─
check_vcd.py
Python
│ └─
simulate.sh
Shell
└─
SKILL.md
Markdown
依赖分析 1 项
| 包名 | 版本 | 来源 | 已知漏洞 | 备注 |
|---|---|---|---|---|
vcdvcd | * | pip | 否 | Open-source VCD parser library; version not pinned but no known vulnerabilities |
安全亮点
✓ All shell execution is explicitly documented in SKILL.md (VCS, Xrun, Icarus commands)
✓ No credential harvesting or environment variable iteration
✓ No network exfiltration or C2 communication
✓ No obfuscation (base64, eval, atob)
✓ No sensitive file/path access
✓ Uses legitimate open-source EDA tools (Icarus Verilog, slang)
✓ VCD analysis uses well-known open-source Python library (vcdvcd)
✓ No remote script execution (curl|bash, wget|sh)
✓ No supply chain risks - no external dependencies beyond documented pip install